The rapidly growing demand for higher performance integrated circuits (ICs) has pushed the boundaries of photolithography to the nanometer scale, which has proven to be the limiting factor to further increasing the performance of ICs. On the other hand, multilayer stacking has shown to be a promising economical and reliable way to increase the transistor density in ICs and, hence, increase their overall performance. In recent years, for example, flash memory manufactures have started to produce three-dimensional multilayer NAND flash chips that will enable solid-state drives (SSDs) to reach terabyte levels at reasonable costs in the foreseeable future. Therefore, three-dimensional multilayer semiconductor devices (MLS) are considered to be the most significant advancement of very-large-scale integration (VLSI), and they will be an essential technology in the semiconductor industry for decades to come.
In semiconductor manufacturing, failure detection or identification of defect positions is an essential process for guaranteeing the reliability of the product and improving its yield. Therefore, failure detection techniques should be developed parallel to the advancements in semiconductor manufacturing. The first step to identify a fault in a defective chip is to determine its rough location (10−3 meter order) with a nondestructive technique, such as Lock-in Thermography (LIT). Then, a more accurate nondestructive technique is used to detect the location of the fault (10−6 meter order) before proceeding to cut the chip to find the exact location of the fault (10−9 order) with a microscope, such as a Transmission Electron Microscope (TEM). Well-established accurate failure detection techniques include Laser Voltage Imaging (LVI) and Optical Beam Induced Resistance Change (OBIRCH). However, these techniques were initially developed for detecting faults in single-layer semiconductors, and numerous problems arise when trying to apply such techniques to MLS. For example, LVI is a technique based on the analysis of the reflected laser beam, which is usually reflected on the fir transistor layer; therefor LVI is not suitable to detect faults in deep layers of MLS. OBIRCH, on the other hand, is a technique that directs an infrared laser beam onto the chip and measures the electrical resistance change caused by an increase of temperature; the laser-induced electrical resistance changes are significantly different for faulty locations than for functional locations. Even though the infrared light is usually absorbed in the shallow transistor layers (or first layer for a single-laver semiconductor), the accumulated heat in these shallow layers is transported to the deep layer by heat conduction. This process results in an increase of temperature in the deep lavers where faults can exist, and if the temperature rise at a fault is high enough then anomalous electrical resistance changes in MLS could be detected, i.e., the fault location can be determined.